Systems exposed to the harsh environments of space must be able to withstand extreme conditions and operate without losing any of their functions or capabilities. Specifically, space based systems must operate in an environment in which the effects of radiation may compromise the operation of conventional integrated circuits.
Four potential problems may arise due to the effects of radiation. Three of these problems can permanently damage integrated circuits, while the fourth problem may be remedied.
First, total dose radiation caused by the cumulative effects of particles striking an integrated circuit can permanently damage the integrated circuit. Second, the radiation dose rate caused by burst radiation may permanently damage the integrated circuit. Third, displacement damage resulting from nuclear interactions, namely scattering that causes semiconductor defects, can cause permanent damage to integrated circuits. Fourth, single event upsets (SEU or SEUs) can cause a change of state (usually in a memory bit). SEUs do not, however, cause permanent damage.
An SEU is a phenomenon in which radiation impinging upon integrated circuits causes errors, such as changed bits, malfunctions, or failures. The radiation-induced errors in microelectronic circuits are caused when charged particles from radiation belts or cosmic rays lose energy by ionizing the medium through which they pass. These charged particles leave behind electron-hole pairs. SEUs occur when energetic particles deposit charge into memory circuits, causing stored data to change state (i.e., from a “1” to a “0,” or vice versa). The errors are soft errors, and are non-destructive.
An SEU typically appears as a transient pulse in logic or support circuitry, or as bit flips in memory cells or registers. Multiple-bit SEUs may also occur. In a multiple-bit SEU, a single ion hits two or more bits, causing simultaneous errors. A multiple bit SEU cannot generally be corrected by single-bit error detection and correction (EDAC) codes and mechanisms. Traditional EDAC codes are useful strictly for the correction of single bit upsets.
However, as the size of devices and their circuits shrinks, radiation testing establishes that adjacent multiple bit upsets may arise in memory cells, and thereby invalidate traditional, simple EDAC codes. Further, as circuits and transistor volumes shrink, relatively smaller total charges are needed to upset a circuit element. Even protons moving through the circuit may deposit sufficient charge to disrupt sensitive locations.
The most common approach for correcting SEUs is the use of triplicated-redundant information storage or error-checking circuitry. For example, a technique known as “voting logic” can be used to catch and correct potential errors in latches. With this technique, a single latch does not effect a change in bit state; rather, several identical latches are queried, and the state will only change if the majority of latches are in agreement. Thus, a single latch error will be “voted away” by the others.
Previous attempts at detection and correction of multiple bit upsets involved triplication of components, or a revised, complex, and slow EDAC scheme. Previous attempts would triplicate the storage memory used in the field programmable gate array (FPGA), and majority vote between the three, to determine the proper set of data. Other complex algorithms were also developed. However, these algorithms would slow down the run time of the FPGA, in that they required multiple levels of comparison before a definitive final output could be determined.
The term ‘field programmable gate array’ generally refers to semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT, or more complex combinational functions such as decoders or simple math functions.
An FPGA operates by taking a data signal, processing the data through programmed logic, and then outputting a resulting data signal. The device is similar to the gate array. The device is shipped to the user with general-purpose, pre-fabricated metallization, and it may have variable length segments or routing tracks. The device is programmed by turning on switches, which make connections between circuit nodes and the metal routing tracks. The connection may be made by an antifuse, or by a transistor switch (which is controlled by a programmable memory element). The transistor switch may be controlled by an SRAM cell or an EPROM/EEPROM/Flash cell. However, for space based or high-reliable systems, radiation effects are a major concern when using FPGAs.
The present invention solves problems, including but not limited to those discussed above, and provides advantages and aspects not provided by prior systems.